Binary Adder with Fast Ripple Carry.
DEPARTMENT OF THE AIR FORCE WASHINGTON D C
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The patent application describes a binary adder using a sequence of alternating pairs of stages. Each stage has a full adder including an exclusive NOR circuit and a fast ripple carry gate. The carry in signal is fed to a logic gating circuit which becomes a sum output or is inverted and then becomes a sum output. The necessity for inversion is dependent upon gating signals applied to a pair of CMOS transistors, which are derived by the exclusive NOR circuit that is connected to the addend and augend inputs.
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