CMOS Life Suitability Evaluation Program
Final technical rept. Jul 1976-Nov 1978
MCDONNELL DOUGLAS ASTRONAUTICS CO ST LOUIS MO
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The results of a matrix of high-temperature accelerated life tests, 125C life tests, and 250 hour 250C lot acceptance tests were evaluated to determine the reliability of a cross-section of the complementary metal oxide semiconductor CMOS family of devices. The devices evaluated included a NOR gate, a flip-flop, a four bit adder, and a counterdivider. Each device was procured from two different manufacturers, and from three different lots of each manufacturer. The correlation of the Lot Acceptance data with the reliability of the devices revealed that the Class S Lot Acceptance Test, as specified in MIL- STD-883, Method 500.5 is approximately 50 effective screening for lot reliability. To minimize the possibility of rejecting good lots andor accepting bad lots, two temperature Lot Acceptance Test is recommended. Using a two temperature Lot Acceptance Test at temperature above 200 C would permit control of both the activation energy and pre-exponential factor in the Arrhenius model. A 100 burn-9n is also recommended. Although burn-in would not improve all lots, it would improve the reliability of those lots which have a freak population with a high failure rate.
- Electrical and Electronic Equipment