Integrated Injection Logic Technology Development
Interim rept. 9 Jun 1975-8 Feb 1976
NORTHROP RESEARCH AND TECHNOLOGY CENTER PALOS VERDES PENINSULA CA
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This report describes the progress in a program to determine the characteristics and limitations of the bipolar integrated injection logic technology as applied to the problem of implementing low power, large scale random logic arrays with low fabrication costs. The activity has concentrated in four areas of integrated injection logic study and development. First, a device and circuit modeling task was undertaken to derive analytical expressions for integrated injection logic design parameters including transistor current gain, fanout, minimum propagation delay, and delay-power product. The calculated properties of integrated injection logic logic gates fabricated on epitaxial wafers as well as uniformly doped nonepitaxial wafers are summarized. Second, the integrated injection logic fabrication process was re-evaluated on optimizing the current gain of npn and pnp transistors. The experimental approach was concentrated on the use of a two-step boron diffusion process for increasing the pnp injection efficiency at no loss in npn current gain. Third, a test chip incorporating the two-step boron diffusion process was designed to obtain experimental measurement of integrated injection logic logic gates used to implement typical random logic functions, such as binary counters and serial shift registers. Fourth, a set of preliminary test results was summarized for devices fabricated with the same set of photomasks on epitaxial as well as nonepitaxial wafers.
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