Design of Radiation Hardened MNOS Memory
Final rept. 15 Jun 1973-30 Jun 1974
SPERRY RAND CORP GREAT NECK NY SPERRY GYROSCOPE
Pagination or Media Count:
This final report covers work performed in designing a CMOSSOS memory subsystem based upon given specifications for a 256-bit memory chip. The subsystem interfaces with the Survivable MOS Array Computer SMARC. Logic design and interconnection for the subsystem are presented herein. So too are the designs and specifications for the three chip types which satisfy all subsystem functions. In addition, the report presents estimates of the producibility and reliability for these chips for both conventional and hardened gate insulators.
- Electrical and Electronic Equipment
- Computer Hardware
- Nuclear Radiation Shielding, Protection and Safety