Design and Demonstration of a 30 GHz 16-bit Superconductor RSFQ Microprocessor
Final rept. 29 Oct 2009-28 Jan 2017
STATE UNIV OF NEW YORK AT STONY BROOK
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The major objective of the project was to design and demonstrate operation of key components of a 30 GHz 16-bit RSFQ processor prototype implemented with the AISTISTEC 10 kAcm sq. fabrication process. Our team has developed complete logical and physical designs of five RSFQ chips using the CONNECT cell library and RSFQ CAD tools developed at the Universities of Yokohama and Nagoya Japan. The major results are the worlds first successful design, fabrication, and demonstration of correct operation of a 20 GHz 8x8-bit parallel carry-save RSFQ multiplier with approximately 6K JJs, a 16-bit sparse-tree wave-pipelined RSFQ adder with approximately 10K JJs, and partial operation of an 8-bit ALU chip with approximately 9K JJs. The goal of the second phase of the project was to get detailed understanding of the performance, complexity, and energy efficiency of on-chip storage units implemented with superconductor Reciprocal Quantum Logic RQL using our RQL VHDL cell library tuned to the MIT Lincoln Laboratory 10 kAcm2 248 nm process. The 8.5 GHz 1-4 Kbit 32-64-bit multi-ported scratchpad memory, register files, write-through and write-back caches designed with RQL Non-Destructive Read-Out storage cells have the average energy consumption of 3.0-9.5 fJbitoperation at room temperature using the cryocooling efficiency of 0.1.
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