Exploration and Evaluation of Nanometer Low-power Multi-core VLSI Computer Architectures
Final rept. Sep 2011-Sep 2014
OKLAHOMA STATE UNIV STILLWATER
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The research objectives of this work are placed on designing a complex Very Large Scale Integration VLSI multi-core architecture using an elaborate design flow or sequence of steps. Many of these architectures are currently or will be employed in advanced architectures that may have secure capabilities within the Air Force Research Laboratory in Rome, NY. This will be accomplished by designing complete design flow integration with commercial and open-source Electronic Design Automation tools. The design flow will take as inputs a high-level system-level architecture description, along with area, critical path delay, and power dissipation constraints. Based on the System on Chip architecture description and design constraints, the tools will automatically generate synthesizable Hardware Descriptive Language HDL models, embedded memories, and custom components to implement the specified VLSI architecture. Results show several orders of magnitude improvement over previous approaches with respect to designs for multi-core architectures, power dissipation strategies, and software reutilization.
- Electrical and Electronic Equipment
- Computer Programming and Software
- Computer Hardware