Batteryless Electroencephalography (EEG): Subthreshold Voltage System-on-a-Chip (SoC) Design for Neurophysiological Measurement
Final rept. 1 Oct 2013-30 Sep 2014
ARMY RESEARCH LAB ABERDEEN PROVING GROUND MD HUMAN RESEARCH AND ENGINEERING DIRECTORATE
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There is a strong need for real-world neuroimaging tools that could provide the hardware substrates supporting the rapidly expanding work in developing optimized brain computer interactive technologies in a fieldable format. It may be possible to support these needs with electroencephalography EEG however, current designs require too much power for long-term operation. Nonconventional, ultra-low power design will be necessary to achieve wear and forget systems for on-line, long-term neurological monitoring. One challenge to this goal is the relatively large dynamic range of EEG relative to a comparably low signal-to-noise ratio this report demonstrates the initial design, simulation, and validation of an EEG data-acquisition, single-integrated-circuit system design that addresses this challenge using an analog front end that adapts on-line to keep the digitized signal within a much smaller dynamic range. This is accomplished through a combination of a voltage-offset controller, low-noise amplifier, low-bit rate analog-to-digital conversion, and a hardware-accelerated digital processor consuming less than 300 nW per channel. At that consumption, it is very feasible to design an entire system capable of operating solely on locally harvested power. Follow-up simulations demonstrate the approaches described here should still provide sufficient signal quality for targeted state monitoring applications.
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