Accession Number:

ADA611687

Title:

TLB for Free: In-Cache Address Translation for a Multiprocessor Workstation

Descriptive Note:

Technical rept.

Corporate Author:

CALIFORNIA UNIV BERKELEY DEPT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES

Personal Author(s):

Report Date:

1985-05-13

Pagination or Media Count:

39.0

Abstract:

In the design of SPUR, a high-performance multiprocessor workstation, the need for large snooping caches suggests a new approach to virtual address translation. By performing this translation in each processors virtual cache, the need for separate translation lookaside buffers is eliminated. Trace-driven simulations show that normal cache behavior is only minimally effected, and that unless an extremely large and complex TLB were built, using a separate device would actually reduce system performance.

Subject Categories:

  • Computer Systems

Distribution Statement:

APPROVED FOR PUBLIC RELEASE