Multiple-Valued PLA Minimization by Concurrent Multiple and Mixed Simulated Annealing
NAVAL POSTGRADUATE SCHOOL MONTEREY CA DEPT OF ELECTRICAL AND COMPUTER ENGINEERING
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We analyze simulated annealing applied to multiple-valued programmable logic array MVL PLA design. Of specific interest is the use of parallel processors. We consider the use of loosely-coupled, coarse-grained parallel systems, and study the relationship between the quality of the solution and computation time, on the one hand, and simulated annealing parameters, start temperature, cooling rate, etc., on the other. We also investigate simulated annealing where there is a mixture of move types. The mixed move approach provides improvement in both the number of product terms and computation time.
- Electrical and Electronic Equipment
- Manufacturing and Industrial Engineering and Control of Production Systems