Accession Number:

ADA584722

Title:

Nano-Electro-Mechanical (NEM) Relay Devices and Technology for Ultra-Low Energy Digital Integrated Circuits

Descriptive Note:

Doctoral thesis

Corporate Author:

CALIFORNIA UNIV BERKELEY DEPT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE

Personal Author(s):

Report Date:

2013-05-01

Pagination or Media Count:

138.0

Abstract:

Complementary-Metal-Oxide-Semiconductor CMOS technology scaling has brought about an integrated circuits revolution over the past 40 years, due to dramatic increases in IC functionality and performance, concomitant with reductions in cost per function. In the last decade, increasing power density has emerged to be the primary barrier to continued rapid advancement in IC technology, fundamentally due to non-zero transistor off-state leakage. While innovations in materials, transistor structures, and circuitsystem architecture have enabled the semiconductor industry to continue to push the boundaries, a fundamental lower limit in energy per operation will eventually be reached. A more ideal switching device with zero off-state leakage becomes necessary. This dissertation proposes a solution to the CMOS power crisis via mechanical computing. Specifically, robust electro-mechanical relay technologies are developed for digital circuit application. A 4-Terminal 4T relay design is firstly developed. Key technology features include tungsten contacts for high endurance low-thermal-budget p-poly-Si0.4Ge0.6 structure for post-CMOS process compatibility Al2O3 as a reliable insulation material dry release step to mitigate stiction and folded-flexure design to mitigate the impact of residual stress. Fabricated relays show good conductance RON 10 kOhms, abrupt switching behavior sub-threshold swing below 0.1 mVdec, and virtually zero leakage IOFF 10-14 A. Switching delay in the 100 ns range and endurance exceeding 109 onoff cycles is achieved with excellent device yield 95. With relay design and process optimizations, pull-in voltage below 10 V with less than 1 V hysteresis is achieved. Miniaturization reduces the device footprint to 35 micron x 50micron, 10 of the first generation device footprint 120 micron x 150micron. Relays with multiple sourcedrain electrodes and multiple gate electrodes are proposed for increased circuit functionality.

Subject Categories:

  • Electrical and Electronic Equipment

Distribution Statement:

APPROVED FOR PUBLIC RELEASE