Power Mems Development
Monthly status rept. 1-31 Dec 2010
SRI INTERNATIONAL MENLO PARK CA
Pagination or Media Count:
This month in Task 1.1, we processed wafers with the revised Metal 3 and Dielectric masks. We completed the processing of the double-side-polished DSP wafer however, the silicon-on-insulator SOI wafer is on hold due to deep reactive ion etching DRIE processing issues. In Task 1.2, we processed wafers with the new pre-sputter metal deposition process. We diced chips from these wafers and released them using both using hydrogen fluoride HF and buffered-oxide-etch BOE processes. The metals were unaffected in both processes. We then flip-chip bonded the chips and tested the device for switch operation. During testing, we found that all of the actuating silicon Si structures that were tested moved toward the Si substrate instead of the glass electrode and remained stuck to the Si substrate. Further analysis showed switches that were not tested remained released, indicating this occurred as a result of the testing. These data suggest that during testing there is an electric potential established between the plate and the Si substrate that allows the plate to move toward the substrate instead of the electrode on the glass substrate. A 1-micrometers gap between the plate and the substrate allows a small potential to move the plate toward the substrate. We believe this potential occurs due to large contact resistance between the metal contact pad and the substrate, resulting in a voltage at the substrate that is sufficiently large to move the plate. To address this issue, we are designing a mask to etch the Si substrate in the vicinity of the plate to eliminate the substrate potential below the plate.
- Electrical and Electronic Equipment