Examination of Multi-Core Architectures
Interim technical rept. Feb-Jul 2010
AIR FORCE RESEARCH LAB ROME NY INFORMATION DIRECTORATE
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This multi-task research effort is designed to determine the applicability of various multi-core architectures to USAF warfighter needs. Furthermore, the resulting advancements in the area of high performance computing will benefit the mission areas of the Air Force Research Lab Information Directorate. This effort is broken down into four tasks the first three tasks include investigating multi-core architectures, benchmarking and performance analysis techniques, and warfighter needs. The final task of the effort combines results from previous tasks and is the design and implementation of an experiment that will compare and contrast multi-core architectures based on their strengths, weaknesses, and applicability to US Air Force C4ISR needs. While there are a great number of multi-core architectures on the market, the first task of the effort aimed specifically at investigating architectures. The system specifications that were examined include the architecture design and performance specifications. For the architectures that were examined, the corresponding software development environment was also examined in greater detail determining characteristics such as tool chains, programming models, and libraries. This technical memorandum serves as a point of reference for information on various multi-core architectures. The research for this report was done as part of an associated support task, JON HPCCINH1, under the RIDER project.
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