Accession Number:

ADA513862

Title:

A Study of the Influence of the POWER5 Dynamic Resource Balancing (DRB) on Optimal Hardware Thread Priorities

Descriptive Note:

Corporate Author:

TEXAS UNIV AT EL PASO

Report Date:

2009-01-01

Pagination or Media Count:

9.0

Abstract:

Simultaneous Multithreading, often abbreviated SMT, is a technique for improving the overall efficiency of superscalar processors with hardware multithreading. SMT permits a processor to concurrently execute multiple independent instruction streams every clock cycle, potentially improving processor throughput. However, this can introduce contention for shared resources amongst threads running concurrently in SMT mode. In order to enable the programmer to control the ratio in which resources are shared, the IBM POWER5 processor allows prioritization of one thread over another. The processor also implements Dynamic Resource Balancing DRB hardware, which throttles back a thread that monopolizes architectural resources by reducing its thread priority. Unlike thread priorities, the DRB is not tunable by software. In this paper, the hardware thread priorities that give best processor throughput are referred to as optimal hardware thread priorities.

Subject Categories:

  • Computer Programming and Software
  • Computer Hardware
  • Mechanics

Distribution Statement:

APPROVED FOR PUBLIC RELEASE