Galvanic Corrosion in Silicon Microsystems: Finite Element Simulation Tool Development
Final rept. 1 Aug 2006-31 Jul 2009
COLORADO UNIV AT BOULDER OFFICE OF CONTRACTS AND GRANTS
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Many microsystems fabrication technologies currently employ a metallic overlayer, such as gold, in electrical contact with silicon Si structural layers. During postprocessing in hydrofluoric acid based solutions, a galvanic cell is created between the silicon and the metallic layer. As a consequence, autonomous corrosion etching of the silicon layer occurs forming nanoscale porosity at the thin film surface and grain boundaries. Over the past 24 months, our ARO sponsored work on microfabricated polycrystalline silicon polySi and single crystal Si SCS shows that electrochemical corrosion can significantly degrade key operational characteristics including stiffness, strength, electrical resistance, and surface morphology. Following characterization and quantification of Si corrosion, we have developed a corrosion simulation tool for microsystems that can be used to predict property degradation including modulus and fracture strength. Designers can also use this model to identify corrosion susceptible device geometries, enabling subsequent design alteration to reduce corrosion or limit corrosion to non-critical areas of the device. The end goal of this research effort being the realization of unprecedented material properties and performance in Si based MEMS through rational design, testing, and simulation.
- Properties of Metals and Alloys
- Numerical Mathematics
- Electrical and Electronic Equipment