Accession Number:

ADA509333

Title:

Optimization of Cyclostationary Signal Processing Algorithms Using Multiple Field Programmable Gate Arrays on the SRC-6 Reconfigurable Computer

Descriptive Note:

Master's thesis

Corporate Author:

NAVAL POSTGRADUATE SCHOOL MONTEREY CA

Personal Author(s):

Report Date:

2009-09-01

Pagination or Media Count:

122.0

Abstract:

This thesis implements a cyclostationary estimation technique called the time-smoothing FFT accumulation method on a reconfigurable computer to generate a frequency vs. cycle frequency approximation of the input signal. This signal processing method can be used to identify signal modulation type and extract the parameters of low probability of intercept signals in electronic intelligence discrimination receivers. This implementation builds on previous work at the Naval Postgraduate School and focuses on reducing the overall runtime to approach real-time processing. The focus of the implementation is to utilize dual field programmable gate arrays FPGAs within a single multi-adaptive processor MAP. Hardware decisions are made by analyzing the relationships between frequency resolution, Grenanders Uncertainly Condition and desired cycle frequency resolution. Implemented on the SRC-6 reconfigurable computer utilizing Xilinx Virtex 2 FPGAs, this work uses the cyclostationary algorithm and takes advantage of the techniques for which the SRC-6 is optimized, such as pipelining, array processing and memory access techniques.

Subject Categories:

  • Computer Programming and Software

Distribution Statement:

APPROVED FOR PUBLIC RELEASE