Fault Tolerant Microcontroller for the Configurable Fault Tolerant Processor
NAVAL POSTGRADUATE SCHOOL MONTEREY CA
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In this thesis, the design of a fault tolerant microcontroller for the Configurable Fault Tolerant Processor is presented. The Configurable Fault Tolerant processor is a spaceborne Field Programmable Gate Array experiment platform susceptible to Single Event Upsets. Fault tolerance is needed to control the experiment in higher radiation orbits and the microcontroller will offer enhanced functionality for experiments. The 16-bit microcontroller is contained within the resources of a single Field Programmable Gate Array. It includes RAM, microprocessor, FPGA configuration and configuration readback modules, PC104 interface module, and fault detection and correction capabilities. Fault tolerance is implemented via triple modular redundancy and Hamming error correction coding. Complete source code for the microcontroller and C-based compilation tools are included as appendices.
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