CARNEGIE-MELLON UNIV PITTSBURGH PA SCHOOL OF COMPUTER SCIENCE
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This thesis presents a compilation framework for translating ANSI C programs into hardware dataflow machines. The framework is embodied in the CASH compiler, a Compiler for Application-Specific Hardware. This style of computation is dubbed Spatial Computation. The first part of this document describes Pegasus, the internal representation of CASH. The most notable of these are a new optimal register-promotion algorithm and partial redundancy elimination for memory accesses based on predicate manipulation. The second part of this document evaluates the performance of the generated circuits using simulation. Using media processing benchmarks, we show that for the domain of embedded computation, the circuits generated by CASH can sustain high levels of instruction level parallelism. A comparison of Spatial Computation and superscalar processors highlights some of the weaknesses of our model of computation, such as the lack of branch prediction and register renaming. The results presented in this document can be applied in several domains 1 most of the compiler optimizations are applicable to traditional compilers for high-level languages 2 CASH itself can be used as a hardware synthesis tool directly from C sources 3 the compilation framework we describe can be applied to the translation of imperative languages 4 we have extended the dataflow machine model to encompass predication, data-speculation and control-speculation and 5 the tool-chain described can be used for synthesis and optimization of asynchronous hardware.
- Computer Programming and Software
- Computer Hardware