Using Heterogeneous High Performance Computing Cluster for Supporting Fine-Grained Parallel Applications
Final technical rept. Feb 2005-Jan 2006
STATE UNIV OF NEW YORK AT BINGHAMTON DEPT OF COMPUTER SCIENCE
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The use of a heterogeneous cluster comprised of host processors and Field Programmable Gate Arrays FPGAs was investigated for accelerating the performance of parallel fine-grained applications using a direct FPGA to FPGA communication channel. The communication channel is implemented with an all-to-all board that attaches directly to the FPGA boards via their IO interface. Test scripts were written to test the all-to-all board. The necessary communication support was designed, tested, and implemented to allow message exchange over the all-to-all board. The all-to-all support provides a low latency, low-bandwidth, communication channel for the FPGAs that can considerably extend the range of parallel applications. The Parallel Discrete Event Simulation was used to demonstrate that this computing model can accelerate the performance of parallel applications.
- Computer Hardware
- Computer Systems Management and Standards