Accession Number:

ADA459612

Title:

Procedural Layout of a High-Speed Floating-Point Arithmetic Unit

Descriptive Note:

Master's thesis

Corporate Author:

MASSACHUSETTS INST OF TECH CAMBRIDGE RESEARCH LAB OF ELECTRONICS

Personal Author(s):

Report Date:

1985-06-01

Pagination or Media Count:

118.0

Abstract:

This thesis presents a case study in the procedural design of the layout of a complex digital circuit. This is the task of writing a program which constructs a VLSI circuit layout given a set of variable parameters which specify the desired functionality of the circuit. We present a set of techniques for guaranteeing that the constructed circuit obeys the geometric and electrical design rules imposed by the underlying circuit technology. These include a set of simple circuit forms and composition rules for building precharged combinatorial circuits which are free of critical race conditions and charge-sharing problems. As an example, we carry out the creation of a program for building a floating-point addition unit which has selectable number of bits of exponent and fraction in the floating-point representation. The high-level design of a companion floating-point multiplication unit is also discussed.

Subject Categories:

  • Electrical and Electronic Equipment
  • Computer Programming and Software

Distribution Statement:

APPROVED FOR PUBLIC RELEASE