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Matter: Modular Adaptive Technology Targeting Efficient Reasoning

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Final technical rept. Dec 2004-Nov 2005

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The objective of this effort was to investigate novel computer architectures to support machine learning, based on reconfigurable hardware and nanowire growth. The scope of this effort was to bring revolutionary architectural ideas together with application drivers that embody cognitive processing dimensions such as machine learning, large knowledge bases, information security and integrity, real-world reasoning, sensor integration and real time embedded systems. Conventional processing architectures are ill-suited to processing the large, sparse, graph data structures necessary to efficiently represent cognitive information and computations. Todays silicon hardware can support a large number of parallel operations and high bandwidth and low latency from small, distributed memories. However, traditional von Neumann architectures employ a single-memory, single-instruction stream model that prevents them from fully exploiting the hardware capabilities. This mismatch presents an opportunity to design new hardware architectures that will provide substantially better performance on graph-intensive information processing tasks, which can perform parallel operations over large data structures. To support these tasks while exploiting the silicon, the MATTER architecture described in this report distributes the data structure over a large number of small, fast memories, and associates active logic with each fragment so that it can perform the necessary operations on its local data. In addition this report describes the exploration into nanowire technology, focusing on the growth of new connections. This is a unique capability of nanowire implementations, which could provide a mechanism for adaptation over time.

Subject Categories:

  • Electrical and Electronic Equipment
  • Computer Programming and Software
  • Computer Hardware
  • Cybernetics

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