Accession Number:

ADA445617

Title:

Algorithm-Based Low-Power Transform Coding Architectures. Part 2. Logarithmic Complexity, Unified Architecture, and Finite-Precision Analysis

Descriptive Note:

Technical research rept.

Corporate Author:

MARYLAND UNIV COLLEGE PARK INST FOR SYSTEMS RESEARCH

Personal Author(s):

Report Date:

1995-01-01

Pagination or Media Count:

33.0

Abstract:

In the companion paper, we addressed the low-power DCTIDCT VLSI architectures of linear complexity increase based on the multirate approach. In this paper, we will discuss other aspects of the low-power design. Firstly, we consider the design of low-power architectures that can lower the power consumption at only Olog M increase in hardware complexity. Next, we will extend the low-power DCT design to other orthogonal transforms such as Modulated Lapped Transform MLT and Extended Lapped Transform ELT. A unified programmable IIR low-power transform module, which can perform most of the existing discrete sinusoidal transforms, is also proposed. Finally, we perform the finite-precision analysis of the DCT architecture under the normal and multirate operations. In VLSI design, the assignment of the system word length will directly affect the total switching events and routing capacities, hence the power consumption. Using the analytical results, we can choose the optimal word length for each DCT channel under required signal-to-noise ratio SNR constraint. The material presented in this paper, together with the multirate architectures in the companion paper, provides a framework for the algorithm-based low-power transform coding kernel design.

Subject Categories:

  • Numerical Mathematics
  • Computer Hardware

Distribution Statement:

APPROVED FOR PUBLIC RELEASE