Accession Number:

ADA443355

Title:

Symmetrical Residue-to-Binary Conversion Algorithm, Pipelined FPGA Implementation, and Testing Logic for Use in High-Speed Folding Digitizers

Descriptive Note:

Master's thesis

Corporate Author:

NAVAL POSTGRADUATE SCHOOL MONTEREY CA

Personal Author(s):

Report Date:

2005-12-01

Pagination or Media Count:

85.0

Abstract:

The robust symmetrical number system RSNS can play a significant role in the reduction of encoding errors within a low-power folding analog-to-digital converter ADC. A key part of this ADC design is the logic block that converts the symmetrical residues from each channel into a more convenient binary output. This thesis describes a robust symmetrical residue-to-binary conversion algorithm for moduli m1 7, m2 8, and m3 9 ADC dynamic range M 126. Also described is a pipelined digital logic implementation for use in high speed programmable logic or application specific integrated circuits. To verify correct outputs of the robust symmetrical residue-to-binary conversion algorithm, a digital test circuit is described that generates the thermometer code symmetrical residues for the 3-channel ADC design.

Subject Categories:

  • Computer Hardware

Distribution Statement:

APPROVED FOR PUBLIC RELEASE