Transistor Sizing of Energy-Delay-Efficient Circuits
CALIFORNIA INST OF TECH PASADENA DEPT OF COMPUTER SCIENCE
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This paper studies the problem of transistor sizing of CMOS circuits optimized for energy-delay efficiency, i.e., for optimal Etn where E is the energy consumption and t is the delay of the circuit, while n is a fixed positive optimization index that reflects the chosen trade-off between energy and delay. We propose a set of analytical formulas that closely approximate the optimal transistor sizes. We then study an efficient iteration procedure that can further improve the original analytical solution. Based on these results, we introduce a novel transistor sizing algorithm for energy-delay efficiency.
- Electrical and Electronic Equipment
- Numerical Mathematics
- Solid State Physics