Accession Number:

ADA433447

Title:

An Efficient Architecture for Ultra Long FFTs in FPGAs and ASICs

Descriptive Note:

Briefing charts

Corporate Author:

DILLON ENGINEERING INC EDINA MN

Personal Author(s):

Report Date:

2004-09-30

Pagination or Media Count:

18.0

Abstract:

This presentation outlines an architecture for efficient Ultra Long FFTs for use in FPGAs and ASICs. Analysis of accuracy, performance, cost and power consumption are presented. FFTs are at the heart of many real time signal processing applications and Ultra Long FFTs are quite often used for frequency analysis and communications applications. As the processing requirements increase, the use of FPGAs and ASICs become the logical choice for implementing real time FFTs. This presentation describes an efficient framework for implementing the Cooley-Tukey algorithm for Ultra Long FFTs using minimal external memory. Typically for lengths over 16K the memory resources of the FPGA or ASIC are exhausted and external memory is required. The architecture is implemented using two shorter length FFTs lengths Nsub1 and Nsub2 to calculate an FFT of length NNsub1 x Nsub2. This architecture is optimized for continuous data FFTs, minimizing the external memory requirements and offering flexibility so that it can be used for many different applications.

Subject Categories:

  • Electrical and Electronic Equipment
  • Computer Hardware
  • Numerical Mathematics

Distribution Statement:

APPROVED FOR PUBLIC RELEASE