Accession Number:

ADA433161

Title:

Versatile Tiled-Processor Architectures: The Raw Approach

Descriptive Note:

Briefing charts

Corporate Author:

MASSACHUSETTS INST OF TECH CAMBRIDGE ARTIFICIAL INTELLIGENCE LAB

Report Date:

2004-09-30

Pagination or Media Count:

33.0

Abstract:

This presentation will describe the Raw architecture, its implementation, and performance. We will focus on Raws ability to support a diverse set of applications ranging from desktop to embedded workloads and multiple forms of parallelism including instruction-level parallelism ILP for desktop applications, and stream parallelism for embedded computing as represented by the VersaBench suite. We will also report detailed performance measurements that quantify the versatility of Raw compared to some widely deployed architectures. As a prelude, the measured versatility of the Raw processor is 0.7, while that of the Pentium III is 0.1. The Pentiums relatively poor performance on stream benchmarks hurts its versatility. Although Raws versatility is better in comparison, the VersaBench suite highlights two clear areas that merit additional research. The first is in improving the architecture to better support embedded bit-level workloads ASICs perform 2x-3x better than Raw. Another area of research focuses on desktop integer applications Raws performance is 2x lower than a Pentium III for applications with low degrees of ILP.

Subject Categories:

  • Computer Programming and Software
  • Computer Systems Management and Standards
  • Computer Hardware

Distribution Statement:

APPROVED FOR PUBLIC RELEASE