Accession Number:

ADA416255

Title:

Test Generation for Very High-Level Design Language (VHDL) Specifications Used in Avionics

Descriptive Note:

Final rept. 27 Jun 1997-10 May 1999

Corporate Author:

HOWARD UNIV WASHINGTON DC ARCHITECTUREAND COMPUTER SCIENCES

Personal Author(s):

Report Date:

2002-08-01

Pagination or Media Count:

45.0

Abstract:

This report describes a technique that automatically generates test pattern sequences for digital systems based on VHDL inputs. This research aims to design a method for detection and elimination of inconsistencies in the Extended Finite State Machine EFSM directed graph model of the VHDL by splitting the graph vertices and duplicating the edges minimally. It focuses mainly on detection and removal of condition-to- condition and action-to-action inconsistencies. Section 1 describes the general problem and lists different tools that already exist. Section 2 describes the algorithm for detection and removal of condition-to- condition inconsistencies. Section 3 presents a pseudocode of the combined detectionremoval condition-to- condition inconsistencies. Section 4 describes the algorithm for detection and removal of action-to-action inconsistencies. Section 5 presents a pseudocode of the combined detectionremoval action-to-action inconsistencies. Section 6 describes the implementation of the algorithm in C along with some examples.

Subject Categories:

  • Computer Programming and Software

Distribution Statement:

APPROVED FOR PUBLIC RELEASE