Power Estimation and Synthesis for Low Power
Final rept. 22 Mar 1995-30 Apr 1999
PURDUE UNIV LAFAYETTE IN SCHOOL OF ELECTRICAL AND COMPUTER ENGINERING
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This document is the final report of the Power Estimation and Synthesis for Low Power. It describes the contributions and achievements of this project. The project explored a wide variety of techniques related to the design of low power CMOS electronic circuits. It explored power estimation techniques, synthesis techniques, macro level design techniques, and low power CMOS logic families. A number of computer-aided design algorithms were implemented to support the various techniques.
- Electrical and Electronic Equipment