Accession Number:

ADA409320

Title:

CMOS Compatibility of a Micromachining Process Developed for Semiconductor Neural Probe

Descriptive Note:

Corporate Author:

SEOUL NATIONAL UNIV (REPUBLIC OF KOREA) SCHOOL OF ELECTRICAL ENGINEERING

Personal Author(s):

Report Date:

2001-10-25

Pagination or Media Count:

5.0

Abstract:

Neural probes are made on silicon substrate using a micromachining process with low temperature steps only. A deep silicon etch Boschh process was used for the probe shaping. CMOS compatibility of the process was checked and reported in this paper. Test transistor patterns generated using standard CMOS fabrication line were exposed to a post-CMOS probe making process including dielectric deposition, gold metalization and the dry etching step, while changes of test transistor characteristics were monitored.. Threshold voltage was found virtually unchanged for both n- and p-type MOS transistors. When excess plasma exposure was done, however, non-trivial shift in p-MOS threshold was observed.

Subject Categories:

  • Anatomy and Physiology
  • Electrical and Electronic Equipment

Distribution Statement:

APPROVED FOR PUBLIC RELEASE