A Fixed-Point Phase Lock Loop in a Software Defined Radio
NAVAL POSTGRADUATE SCHOOL MONTEREY CA
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A software defined radio is a much more flexible platform than traditional, hardware implemented radios, By implementing radio functions in software, and putting those functions on a Field Programmable Gate Array FPGA chip, users will have the ability to download mission specific radio capabilities. This thesis examines a fundamental piece of the receiver, the Phase-Lock Loop PLL, simulates a software PLL, and investigates the effects of fixed-point versus floating point mathematics required for an FPGA based PLL. With a fixed-point PLL simulator, figures of merit such as lock-time, lock range, and pull-in range are determined for typical signal-to-noise ratio SNR levels.
- Computer Programming and Software
- Radiofrequency Wave Propagation
- Radio Communications