Accession Number:

ADA407041

Title:

A Fixed-Point Phase Lock Loop in a Software Defined Radio

Descriptive Note:

Master's thesis

Corporate Author:

NAVAL POSTGRADUATE SCHOOL MONTEREY CA

Personal Author(s):

Report Date:

2002-09-01

Pagination or Media Count:

89.0

Abstract:

A software defined radio is a much more flexible platform than traditional, hardware implemented radios, By implementing radio functions in software, and putting those functions on a Field Programmable Gate Array FPGA chip, users will have the ability to download mission specific radio capabilities. This thesis examines a fundamental piece of the receiver, the Phase-Lock Loop PLL, simulates a software PLL, and investigates the effects of fixed-point versus floating point mathematics required for an FPGA based PLL. With a fixed-point PLL simulator, figures of merit such as lock-time, lock range, and pull-in range are determined for typical signal-to-noise ratio SNR levels.

Subject Categories:

  • Computer Programming and Software
  • Radiofrequency Wave Propagation
  • Radio Communications

Distribution Statement:

APPROVED FOR PUBLIC RELEASE