Feasibility Analysis and Design of a Fault Tolerant Computing System: A TMR Microprocessor System Design of 64-Bit Cots Microprocessors
NAVAL POSTGRADUATE SCHOOL MONTEREY CA
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The purpose of this thesis is to analyze and determine the feasibility of implementing a fault tolerant computing system that is able to function in the presence of radiation induced Single Event Upsets SEU by using the Triple Modular Redundancy TMR technique with 64-bit Commercial-Off-The-Shelf COTS microprocessors. Due to the radiation environment in space, electronic devices must be designed to tolerate the radiation effects. While there are radiation-hardened devices that can tolerate radiation effects, they offer lower performance and higher cost than COTS devices. On the other hand, COTS devices offer lower cost, orders of magnitude higher performance, shorter design time and better software availability and compatibility. However, COTS devices are susceptible to the radiation effects. In order to use COTS devices in space environment, a fault tolerance technique such as TMR needs to be implemented. This thesis presents the design and analysis of a TMR 64-bit COTS microprocessor implementation. The system incorporates three 64-bit microprocessors, the memory system including SRAM and PROM memory modules and the programmable logic devices that are used to implement the IMR technique. The validity of the design is verified by the timing analysis conducted on read and write operations.
- Computer Programming and Software