A Reconfigurable Computing Architecture for Microsensors
ARMY RESEARCH LAB ADELPHI MD
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Users desire microsensors that support reconnaissance, surveillance and target acquisition RSTA operations. Typically, the communications bandwidth on these microsensors limits the amount of data that can be transmitted. Therefore, much of the signal processing must be performed within the aggressive size, power, and weight constraints of the microsensor. Furthermore, these microsensors need to be inexpensive and have a very small logistics tail. Low-power ASIC technology can address the performance and power issues but may not be reusable over a wide range of applications. Programmable processors DSPs, and Microprocessors may provide the flexibility but not necessarily the performance. A new paradigm is sought to provide low-power, high-performance, reprogrammable computing. To ensure low expense, a common and open architecture should be developed. This will allow the cost to be shared among the widest range of applications possible while allowing for technology upgrades. This paper describes the development of a computing architecture which uses a general purpose processor combined with field programmable gate array technology FPGA that can be used to accelerate a range of microsensor applications. We have demonstrated two orders of magnitude reduction in size, weight, and power over an existing Army Research Laboratory testbed.
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