Accession Number:

ADA386424

Title:

Completion and Testing of a TMR Computing Testbed and Recommendations for a Flight-Ready Follow-On Design

Descriptive Note:

Master's thesis

Corporate Author:

NAVAL POSTGRADUATE SCHOOL MONTEREY CA

Personal Author(s):

Report Date:

2000-12-01

Pagination or Media Count:

172.0

Abstract:

This thesis focuses on the completion and hardware testing of a fault tolerant computer system utilizing Triple Modular Redundancy TMR. Due to the radiation environment in space, electronics in space applications must be designed to accommodate single event phenomena. While radiation hardened processors are available, they offer lower performance and higher cost than commercial off the shelf processors. In order to utilize non-hardened devices, a fault tolerance scheme such as TMR may be implemented to increase reliability in a radiation environment. The design that was completed in this effort is one such implementation. The completion of the hardware design consisted of programming logic devices, implementing hardware design corrections, and the design of an overall system controller. The testing effort included basic power and ground verification checks to programming, executing, and evaluating programs in read only memory. During this phase, additional design changes were implemented to correct design flaws. This thesis also evaluated the preliminary design changes required for a space implementation of this TMR design. This included design changes due to size, power, and weight restrictions. Additionally, a detailed analysis of component survivability was performed based on past radiation testing.

Subject Categories:

  • Computer Programming and Software
  • Unmanned Spacecraft

Distribution Statement:

APPROVED FOR PUBLIC RELEASE