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Design Optimization of a GaAs RISC Microprocessor with Area-Interconnect MCM Packaging
Final progress rept. 27 Sep 1994-1999
MICHIGAN UNIV ANN ARBOR
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This project analyzed Complementary Gallium Arsenide CGaAs and advanced packaging technologies for use in high performance and radiation hard circuits. The basic CGaAs process was analyzed in his project for non-linear design rule scaling. Static, domino and dual-rail domino CVSL circuits were designed to evaluate CGaAs for use in VLSI circuits. Phase-Locked Loop and current-mode 110 circuits were designed and tested. To facilitate the design of systems proposed in this project, a CGaAs cell library, SRAM compiler, and place-and-route tools that support flip- chip area IO packaging were developed. A gold-bumping process was developed in the UM solid-state electronics laboratory which produces bumps on pitches as tight as 50 micrometers. A superscalar PowerPC microarchitecture was developed for implementation in the modest integration levels of CGaAs. The project culminated in the design and testing of the PUMA PowerPC integer processor which incorporates area-IO for flip-chip packaging. Parameter variation in the CGaAs process of the prototype run rendered the unipolar-logic decoder circuits in the SRAMs inoperative nevertheless, most of the processor was functional. This project demonstrated that CGaAs is a viable technology for radiation-hard microprocessors, but it would need to have threshold voltages and minimum geometries scaled to achieve high performance.
APPROVED FOR PUBLIC RELEASE