Embedded and Real-Time Application of High-Performance Scalable Computing.
Final technical rept. Sep 95-Sep 98,
LOCKHEED MARTIN CORP SYRACUSE NY OCEANRADAR AND SENSOR SYSTEMS
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Pre and Post Doppler Space-Time Adaptive Processing STAP architectures were considered for target implementations based on embedded High Performance Scalable Computing HPSC architectures leveraging commercially available processing technology from Analog Devices Super Harvard Architecture SHARC Digital Signal Processor DSP. Algorithm partitioning and mapping was performed that demonstrated initial feasibility and then a sizing study was performed for a theoretical implementation. Further modeling and simulation studies utilized a discrete event simulator to perform detailed timing analysis and three different mappings of the Recursive Modified Gram Schmidt with Error Feedback RMGSEF algorithm in order to obtain insight into processor communication utilization and data latency. This effort culminated in a real time Radar demonstration of the RMGSEF algorithm that was implemented using parallel SHARC processors based on the High Performance Scalable Computer HPSC to perform the QR Decomposition QRD. The demonstration Radar System incorporated 18 antenna elements over three pulse repetition intervals resulting in 34 degrees of freedom with performance of less than 15 ms of latency and a 42KHz sample rate. Further studies concentrated on alternative STAP solutions based on evolving Motorola PowerPCs and Field Programmable Gate Arrays FPGAs.
- Active and Passive Radar Detection and Equipment
- Computer Programming and Software
- Computer Systems