An Improved Asynchronous Implementation of a Fast Fourier Transform Architecture for Space Applications
AIR FORCE INST OF TECH WRIGHT-PATTERSONAFB OH SCHOOL OF ENGINEERING
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A second-generation fully asynchronous Fast Fourier Transform FFT processor for space applications is developed in this thesis. A high-performance patented FFT architecture invented by Suter and Stevens was used as the basis for a 16-point FFT FFT-16 processor design. A brief derivation of the architecture, the asynchronous design methodologies used and space-based integrated circuit issues are presented. The Synopsys VLSI CAD system and a radiation tolerant design library developed by the Air Force Research Laboratory were used to implement the design. A critical building block of the FFT-16, the FFT-4, was fabricated as a cost-effective method to validate the cell library and the applied asynchronous design methodologies before larger point sizes are fabricated. Results from high-fidelity simulations show that the FFT-16 design has an efficiency of 28 nJUnit-Transform and has a worst case throughput of 760 ns. Extrapolating these results to an FFT-1024 gives an estimated efficiency of 120 njUnit-Transform and worst case throughput of 2 microns. These results demonstrate that current space-based FFT processors can be replaced with a design that improves performance and efficiency by two orders of magnitude.
- Electrical and Electronic Equipment