12-Bit High Dynamic Range ADC
Monthly rept. 15 Feb-15 Mar 98
TRW SPACE AND ELECTRONICS GROUP REDONDOBEACH CA
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During this reporting period, detailed layout of the ADC chip and final circuit simulations continued. The attached figure shows a plot of the partially completed chip layout. All signal path cell layouts have been completed. To address manufacturability issues, the chip floorplan was revised slightly, resulting in a reduction in overall chip size by approx. 15 to 4.9 mm x 4.5 mm. Critical blocks are currently being reviewed and layout revision recommendations generated. Block-to-block routing is in progress, and interconnect parasitics are being extracted to enable back-annotation of circuit simulation files. Critical signal paths are then re-simulated and circuit designs adjusted to optimize performance.
- Electrical and Electronic Equipment