Accession Number:

ADA339655

Title:

A Single Chip Low Power Implementation of an Asynchronous FFT Algorithm for Space Applications

Descriptive Note:

Master's thesis.

Corporate Author:

AIR FORCE INST OF TECH WRIGHT-PATTERSONAFB OH

Personal Author(s):

Report Date:

1997-12-01

Pagination or Media Count:

128.0

Abstract:

A fully asynchronous fixed point FFT processor is introduced for low power space applications. The architecture is based on an algorithm developed by Suter and Stevens specifically for a low power implementation. The novelty of this architecture lies in its high localization of components and pipelining with no need to share a global memory. High throughput is attained using large numbers of small, local components working in parallel. A derivation of the algorithm from the discrete Fourier transform is presented followed by a discussion of circuit design parameters specifically, those relevant to space applications. The generic architecture is explained with a survey of the 16 points FFT architecture specific to this project. An implementation, which included a test chip fabricated through MOSIS, is described. Finally, simulation results based on layout extractions are presented and an outline for future work is given.

Subject Categories:

  • Electrical and Electronic Equipment
  • Computer Hardware

Distribution Statement:

APPROVED FOR PUBLIC RELEASE