Accession Number:

ADA339149

Title:

Delay Fault and Stuck-At Fault Test Generation Using Multiprocessing

Descriptive Note:

Final technical rept. Aug 94-Dec 96

Corporate Author:

SYRACUSE UNIV NY SCHOOL OF COMPUTER AND INFORMATION SCIENCE

Personal Author(s):

Report Date:

1997-10-01

Pagination or Media Count:

49.0

Abstract:

Digital logic circuits must be tested to assure their correct behavior at the desired clock rate. This report describes an algorithm for generating tests for path delay faults these faults are models of the faulty switching behavior of digital circuits. The path delay fault test generation system developed here is based on an extension to the Sixteen valued Maximized Propagation Lowered Enumeration SIMPLE algorithm, which was originally developed for stuck-at faults test generation. The extension of SIMPLE resulted in a powerful path delay fault test generator with the ability to identify nearly every non-robustly detectable fault in a circuit without resorting to the enumeration phase. A parallel implementation of the test generator was developed using the Parallel Virtual Machine PVM communication package.

Subject Categories:

  • Electrical and Electronic Equipment
  • Computer Programming and Software

Distribution Statement:

APPROVED FOR PUBLIC RELEASE