Accession Number:

ADA336778

Title:

Single-Event Analysis of LT GaAs Mesfet Integrated Circuits

Descriptive Note:

Master' thesis

Corporate Author:

NAVAL POSTGRADUATE SCHOOL MONTEREY CA

Personal Author(s):

Report Date:

1997-09-01

Pagination or Media Count:

55.0

Abstract:

There is a growing need for the use of electronics in radiation environments such as space. Gallium arsenide GaAs semiconductor technology is highly desirable for these applications because it consumes less power at higher speeds than silicon Si and shows superior radiation hardness over silicon technologies except for Single-Event-Upset SEU. This thesis examines GaAs MESFETs fabricated in the Vitesse H-GaAsIIIR process utilized in Direct Coupled FET Logic DCFL inverters. These simulations are targeted at determining the vulnerability of these devices to SEU. MESFETs fabricated on low-temperature grown GaAs LT GaAs epitaxial layers are investigated in addition to the conventional MESFET process using only bulk GaAs. Two-dimensional computer simulations are performed to determine the most effective method to simulate SEU charge collection mechanisms, and how effective the LT GaAs buffer layer is at reducing SEU vulnerability. This thesis is part of a larger project that is attempting to develop a new wafer design that can be inserted into the current Vitesse fabrication process to produce radiation hardened circuits. Computer simulations are performed using MIXEDMODER, which is a SPICE simulator for the ATLASR device simulation software created by SILVACO International Inc.R.

Subject Categories:

  • Electrical and Electronic Equipment

Distribution Statement:

APPROVED FOR PUBLIC RELEASE