Radiation Hard 0.35 micrometer SOI CMOS Development
Technical progress rept.
HONEYWELL INC PLYMOUTH MN SOLID STATE ELECTRONICS CENTER
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We have started two quick turn DOI lots this month with objectives of completing unit processing required for gate oxide reduction and drain engineering. One five-wafer NMOS DOI lot and one five-wafer PMOS DOI lot were being processed at the same time using 22009883 design for quick turn evaluation of 0.8 micrometr devices with minimum geometry down to 0.5 micrometer Note SSEC has requested a new DOI design in mid-October specifically designed for 0.35 micrometer CMOS. New masks for 0.35 micrometer devices evaluation will be available in November. Electrical assessment of the parameters relevant to 0.35 micrometer CMOS will be evaluated accurately afterward. We have pulled two wafers out of each lot NMOS 9883-466 and PMOS 9883-467 at the silicide step for electrical testing to check for well dopings against process simulation. All other wafers are still in process to complete contact and metal processing. Note the gate oxide was often damaged by probes when silicide layer was used in the gate oxide integrity experiment Voltage ramping at a constant current. The completion of metal layer will allow an investigation of the gate oxide integrity. The gate oxide defect density can be evaluated after the completion of both DOI lots. To date we have no data regarding this important parameter for the 100 A gate oxide. The gate oxide thickness of these two lots was measured to be 99 A. The 99 A gate oxide was grown at 780 deg C in wet oxygen instead of baseline 850 deg C wet oxygen growth. The evaluation of these wafers pulled at the silicide step will enable us to adjust the well dopings of the first baseline 0.35 CMOS lot. Radiation properties of the 99 A gate oxide are being evaluated.
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