SDVS/VHDL Application Program Plan,
AEROSPACE CORP EL SEGUNDO CA ENGINEERING AND TECHNOLOGY GROUP
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This report delineates a plan for accomplishing the SDVSVHDL Application task, an effort on the part of The Aerospace Corporation Aerospace to specify and verify formally properties of a moderate-size hardware description, provided by the National Security Agency NSA, of production integrated circuitry. The description is to be written in the VHSIC Hardware Description Language VHDL, and the specificationverification tool to be used is the State Delta Verification System SDVS. The SDVSVHDL Application will be directed towards demonstrating the suitability of SDVS to the verification of realistic VHDL hardware descriptions, stress-testing SDVS, and formulating strategies for further research and development in formal verification generally, and particularly in VHDL verification. Aerospace and NSA have an ongoing commitment to investigating the utility of formal methods for DoD Programs. In particular, Aerospace continues its multi-year project to build an automated system for formal verification that can be used at all levels of the hierarchy of digital computer systems the State Delta Verification System. The goal is to verify hardware from gate-level designs to high-level architecture, and to verify software from the microcode level to application programs written in high-level programming and hardware description languages.
- Computer Programming and Software
- Computer Hardware