VLSI Testability Synthesis Tool.
Final rept. 13 Apr 93-26 Feb 96,
WRIGHT STATE UNIV DAYTON OH DEPT OF ELECTRICAL ENGINEERING
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The VTST project developed a set of Built-In-Self-Test BIST methodologies and implemented them in the VTST Computer Aided Design CAD toolset. These test methodologies include a pseudo- exhaustive parallel BIST technique that utilizes an efficient test signal reduction method for combinational circuits based on Dr. Chens research. This technique reduces the size of the test pattern generator TPG and the number of test patterns required for a given Circuit Under Test CUT. Dr. Chens method was extended to include methods for testing storage elements, i.e., sequential circuits. The VTST toolset includes a non-scan circular BIST method, full and partial-scan methodologies, and circular BIST combined with pseudo-partial scan. Programs are included for fault simulation, partitioning circuits into subcircuits to improve fault coverage, removing redundant faults, synthesizing BIST circuits, and automatically inserting the BIST circuits into the original circuit. The VTST toolset interfaces with LSI Logics CMDE CAD toolset, generating BlSTed circuits in LSIs NDL format. A VHDL parser is included that allows VHDL designs to be input to VTST VHDL output can also be generated. The tools are hosted on a Sun workstation and permit concurrent engineering use on multiple machines. Several test circuits were processed to verify correct operation.
- Electrical and Electronic Equipment
- Computer Programming and Software