Image Reconstruction Board
Final rept. Jan 1994-Dec 1996
ARMY RESEARCH LAB ADELPHI MD
Pagination or Media Count:
This report describes an image reconstruction board developed as part of an interface requirement for an acousto-optic AO range doppler radar processor, and presents a brief summary of the program for which the board was designed. A description is given of the charge coupled device CCD camera interface in which the board resides, and the boards algorithm and schematic block diagram are discussed. A full set of board-level schematics is given and briefly discussed. The paper also lists and discusses the VHSIC hardware description language VHDL code used to program the field programmable gate arrays FPGAs used in the design. The CAD CAM system used to simulate and build the board is described. VHDL and simulator command files used in the simulation are included. Finally, simulation and hardware test results are presented and compared. Sections 3.2 and 3.3 give detailed descriptions of the electronics schematics and VHDL code. These sections are for the reader who requires a detailed understanding of the electronics of the board the casual reader may wish to skip these sections.
- Active and Passive Radar Detection and Equipment
- Acoustooptic and Optoacoustic Devices