F-RISC - A 1.O GOPS Fast Reduced Instruction Set Computer for Super Workstations and TeraOPS Parallel Processing Applications.
Final rept. 1 Aug 90-31 May 95,
RENSSELAER POLYTECHNIC INST TROY NY CENTER FOR INTEGRATED ELECTRONICS
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A Fast Reduced Instruction Set Computer is designed using the Rockwell 50 GHz Baseline GaAsAlGaAs Heterojunction Bipolar Transistor Process. Tbe goal of the project is a 1OOO NIPS integer RISC engine in the form of a multiple chip integration using MCM technology. Cell libraries and CAD tools for this effort have been created and tested. Test structures have been fabricated and tested which indicate that the general approach is viable, and all architecture chips have been completed. However, certain process deficiencies could lead to circuit performance that is slower than predicted from Rockwell supplied models by a factor of 30-50. In spite of this, work-around strategies have been devised and it is felt that the Rockwell process can still achieve the speed goal of 2 GHz clock operation. These strategies consist of altering the layout of the transistor using a smaller emitter with a larger aspect ratio, and three active edges, and some shortening of base-emitter and base colleccor separations, and variation of the wire geometries or shifting to the third level of metal for them.
- *PARALLEL PROCESSORS
- GALLIUM ARSENIDES
- ALUMINUM GALLIUM ARSENIDES
- COMPUTER ARCHITECTURE
- PARALLEL PROCESSING
- WORK STATIONS
- COMPLEMENTARY METAL OXIDE SEMICONDUCTORS
- ASPECT RATIO
- BIPOLAR TRANSISTORS
- Computer Hardware