Accession Number:

ADA303421

Title:

Synthesis of Timing-Constrained VLSI Systems.

Descriptive Note:

Final rept. 1 Jul 91-14 Oct 94,

Corporate Author:

WASHINGTON UNIV SEATTLE NORTHWEST LAB FOR INTEGRATED SYSTEMS

Report Date:

1995-11-28

Pagination or Media Count:

27.0

Abstract:

Our research investigated the problem of synthesizing timing-constrained systems, with an emphasis on real-time control circuits and communication-intensive systems. Solving the general problem of synthesizing timing-constrained systems requires solutions to subproblems along a broad front from high-level specification to circuit design and implementation. The specific subproblems we investigated were 1 timing specification, analysis and verification, 2 high-performance clocking methodologies, 3 synthesis of reactive embedded systems, and 4 FPGA architectures and design tools for high-performance circuits and interfaces. AN

Subject Categories:

  • Electrical and Electronic Equipment
  • Computer Programming and Software

Distribution Statement:

APPROVED FOR PUBLIC RELEASE