Synthesizing Field Programmable Gate Array Circuitry Using C++.
Final rept. 31 Mar-31 Aug 95,
WRIGHT LAB WRIGHT-PATTERSON AFB OH
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In recent years, systems which use Field Programmable Gate Arrays FPGAs to perform computations have been shown to match or even exceed super computer levels of performance. These FPGA based custom computing machines FCCMs take advantage of an FPGAs gate-level reconfigurability to implement instructions and architectures specific to the problem being solved. The ability to tailor the hardware to a specific problem gives FCCMs a great speed advantage over general purpose processors with fixed instruction sets. Currently, one of the largest obstacles to the use of an FCCM is program or instruction set development. Since an FCCM is programmed at the gate level, the programmer must have detailed knowledge of both the algorithm to be implemented and how to implement necessary operations e.g. addition, subtraction, and multiplication required by the algorithm in the FCCMs hardware. This design process is comparable to programming in assembly language, though hardware instruction design is arguably more difficult. Recent research efforts have investigated the creation of a novel, symbiotic compiler which can simplify the development of programs for FCCMs by hiding the hardware instruction set generation from the programmer in much the same way a traditional compiler isolates the user from a specific machines assembly language. This paper presents the details of the internal operation of this FCCM compiler and plans for future work.
- Electrical and Electronic Equipment
- Computer Hardware