Accession Number:

ADA301446

Title:

Simulation and Analysis of Predictive Read Cache Performance.

Descriptive Note:

Corporate Author:

NAVAL POSTGRADUATE SCHOOL MONTEREY CA

Personal Author(s):

Report Date:

1995-06-01

Pagination or Media Count:

56.0

Abstract:

Efforts to speed up the memory hierarchy have failed to keep up with the rapid increase in microprocessor performance. The use of first-level and second-level caches has become common in an effort to minimize this speed discrepancy. One potential method to overcome the speed problem while using much less hardware than a second-level cache, is the predictive read cache. This thesis continues previous efforts in designing and optimizing the predictive read cache. It develops a method to simulate the performance of a memory hierarchy containing a predictive read cache and uses these simulations to determine the most effective architecture of the cache. Using trace data from an Intel 486 processor running the SPEC benchmarks, the simulations demonstrate that a small predictive read cache can give a performance improvement equivalent to a much larger second-level cache. This makes the predictive read cache ideal for systems that are power or chip area limited.

Subject Categories:

  • Computer Hardware

Distribution Statement:

APPROVED FOR PUBLIC RELEASE