Accession Number:
ADA297723
Title:
Implementation of Error Detection and Correction (EDAC) in the Static Random Access Memory (SRAM) Aboard Petite Amateur Navy Satellite (PANSAT).
Descriptive Note:
Master's thesis,
Corporate Author:
NAVAL POSTGRADUATE SCHOOL MONTEREY CA
Personal Author(s):
Report Date:
1995-03-01
Pagination or Media Count:
95.0
Abstract:
This thesis documents the design of a bus controller that provides EDAC capability to the SRAM of an Intel M8OC 1 86XL Microprocessor running at 7.3728 MHz. The system was designed for use during a two-year mission in a low earth orbit on board PANSAT. The system uses standard CMOS components together with the Harris ACS630MS EDAC circuit to provide dual-bit error detection with single-bit error correction. The single-bit error correction process is transparent to the microprocessor. All single-bit errors detected are automatically corrected in memory during the same bus cycle in which they are detected. The EDAC circuit computes the check bits based upon a 16-bit data word. Byte write capability is provided by using a read-modify-write method. The system was built on a wire wrap development board and tested for proper operation. KAR P. 2
Descriptors:
- *MICROPROCESSORS
- *RANDOM ACCESS COMPUTER STORAGE
- *COMMUNICATION SATELLITES
- *NAVAL EQUIPMENT
- *ERROR CORRECTION CODES
- *ERROR DETECTION CODES
- SOFTWARE ENGINEERING
- DETECTION
- EARTH ORBITS
- LOW ORBIT TRAJECTORIES
- THESES
- TRANSPARENCE
- CYCLES
- READ WRITE MEMORIES
- MISSIONS
- ERRORS
- LIGHTWEIGHT
- STATICS
- ONBOARD
- BUS CONDUCTORS
- CORRECTIONS
- BYTE FUNCTIONAL MODULES
Subject Categories:
- Computer Programming and Software
- Computer Hardware
- Unmanned Spacecraft