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VLSI for High-Speed Digital Signal Processing.
Final rept. 1 Jul 91-30 Sep 94,
CALIFORNIA UNIV LOS ANGELES
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The research supported by this ONR grant has investigated modem high-speed signal processing system design. It has encompassed a complete spectrum of activities, starting with the discovery of new signal processing algorithms, and continuing through the development of the most appropriate methods for their realization, including, in particular, the design, layout and fabrication of integrated circuits. The primary project for this grant has been the design and implementation of a new type of programmable general purpose digital filter IC. It employs multiple processing units on a single integrated circuit. The multiple processors operate in parallel and communicate with one another through on-chip dual-access storage register blocks, thereby incurring no operating speed penalties as would result if it were necessary to read and write to off-chip RAM. The systems topology has the processors arranged in a ring, with locally-shared register blocks between each adjacent pair of processors. Our prototype IC has five processors, and it is capable of realizing a rich variety of filter structures that operate at the maximum instruction execution rate possible for any custom parallel implementation. A circuit board using four of our ring processor chips was also designed and built. It demonstrates the ICs capability to perform real-time video processing and high-speed one-dimensional processing of data. It resides in an rBM PC computer and is accessed through the PC bus. A custom software package was also written that facilitates the programming of the chips and the configuration of the circuit board for each of its several operating modes.
APPROVED FOR PUBLIC RELEASE