Accession Number:

ADA289317

Title:

Accelerating Conservative Parallel Simulation of VHDL Circuits

Descriptive Note:

Master's thesis

Corporate Author:

AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF ENGINEERING

Personal Author(s):

• Hurford, Joel F.

Report Date:

1994-12-01

Pagination or Media Count:

96.0

Abstract:

This research effort considers heuristic and cost model based techniques for the optimal partitioning of VHDL circuits for parallel simulation. Correlation statistics are gathered on a wide variety of graph-based a priori parameters. Linear regression is used to identify significant parameters for inclusion in a representative cost model. Driving a greedy search, this cost model is used to improve upon initial heuristic partitions. The influence of feedback dominated previous research so a no-feedback algorithm is used to create the initial partition The circuits studied range from 1,050 to 4,243 gates.

Descriptors:

• *COMPUTERIZED SIMULATION
• *INTEGRATED CIRCUITS
• CORRELATION
• COST MODELS
• FABRICATION
• FEEDBACK
• HEURISTIC METHODS
• LINEAR REGRESSION ANALYSIS
• PARALLEL PROCESSING
• STATISTICS

Subject Categories:

• Electrical and Electronic Equipment
• Computer Programming and Software

Distribution Statement:

APPROVED FOR PUBLIC RELEASE